The present disclosure generally relates to methodologies for automatically generating three-dimensional device structures corresponding to arbitrary design layouts of semiconductor devices for three-dimensional technology computer aided design (TCAD) device simulations, and a system for implementing the same.
Three-dimensional (3D) technology computer aided design (TCAD) based device simulation is crucial for device modeling for semiconductor devices at semiconductor technology nodes beyond the 45 nm node. 3D TCAD based design simulation can aid in, for example, capacitance extraction, I-V data calibration, and study of 3D effects.
In order for a 3D TCAD based device simulation to be helpful, the physical structure of the device under simulation must be captured accurately in a structure file that lists three-dimensional features of the device under simulation. Specifically, the three-dimensional features include the boundary representation of device, the materials involved, doping profiles, contacts to the device, and mesh geometries over which physical model equations are solved.
Traditional Technology CAD (TCAD) methodologies focus on process simulations in two dimensions and three dimensions to obtain an accurate representation of the device or the structure file. Traditional TCAD methodologies are limited to single or few device instances owing to the computational costs/time intensive nature of process simulation, and hence the structure file for layouts is created manually using approximate doping profiles, etc. This is accomplished either through an interactive graphic user interface (GUI) editor or a script detailing interactions of various bodies and their overlap behavior. Parameterization of the TCAD methodologies is limited.
However, generation of a structure file corresponding to a 3D device structure of any design layout has proven to be a major challenge. Particularly, incorporating the same set of process assumptions for any layout to produce the correct boundary representation of the layout devices has been a tedious and difficult manual process. Further, such manual coding of device structures to generate a structure file has proven to be error prone, labor intensive, and time-consuming because all process layers and geometries need to be accounted for. Thus, generation of a structure file compatible with device simulation has been a significant bottleneck in product development cycles. Further, iterative modification of circuit layouts with feedback from CAD based device simulation has been impractical.
Overall, manual structure file generation is time consuming, error prone, iterative. There is no guarantee that process assumptions for different layouts coded up by different TCAD engineers are the same. Thus, a cumbersome manual check is necessary. In addition, it is difficult to change process assumptions on the fly—i.e., to test the same layout with different versions of process assumptions and/or different evaluation versions. Further, it is extremely hard to deal with generic layouts employing the manual structure file generation method. As a result, electronic design automation (EDA) tools are inefficiently utilized as most of the time is spent in structure coding for the tool rather than using the EDA tools.